`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    16:49:37 12/21/2019 
// Design Name: 
// Module Name:    ShiftReg 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module ShiftReg(
	 input wire clk,
    input wire[1:0] S,
    input wire SL,
    input wire SR,
    input wire[DATA_BITS-1:0] D,
    output reg[DATA_BITS-1:0] Q
    );

    parameter DATA_BITS = 16;
    
    initial Q = 0;
    
    always @(posedge clk) begin
        case (S)
            2'b00: Q <= Q;
            2'b01: Q <= {SR, Q[DATA_BITS-1:1]};
            2'b10: Q <= {Q[DATA_BITS-2:0], SL};
            2'b11: Q <= D;
        endcase
    end


endmodule
